Fuzzy Numbers based on Energy Indicators of Reliability Power System

1Nadheer A. Shalash and 2Abu Zaharin Ahmad

1 Faculty of Engineering of Electrical power techniques

Al-Mamon University college,Baghdad, Iraq

2Faculty of Electrical and Electronics Engineering

University Malaysia Pahang,  26600 Pekan, Malaysia

Abstract

 This paper presents the approach of fuzzy numbers for reliability calculation of electrical energy indices and compared to an analytical method. In this paper, the fuzzy numbers which are represented by triangular fuzzy numbers are used to evaluate the load duration curve and the probabilities capacity generators that are in services, in term of the expected energy not supplied (EENS), loss of energy expectation (LOEE) and the energy index of the reliability (EIR). A case study based on the Malaysia distribution network (DISCO-Net) is carried out.The proposed method shows a simple implementation and the results seem to be a good approximation to the analytical approach.

 Keywords

 Electrical energy indice; fuzzy numbers; daily load; Probability.

1.Introduction

 Recently, many applications of the fuzzy numbers approach to electric power system engineering have been proposed. One of these applications is assessed on reliability generation based on the loss of energy indices. Reliability of the generated power system is afflicted with the load curve characteristics, peak duration and variety between levels of the peak at each hour, day and month of each season of a year. Various kinds of customers might have different load curve charts. The most frequent for electrical loads are for residential, commercial and industrial, which isfor each load curve usually contains a characteristic chart. Probability based models have already been advanced for precisely reflects the stochastic nature of generators behavior and determines its reliability interpretation [1-2]. As a result of the increased demand powers, a small separated system is not able to provide a power with sufficient generation control and an acceptable level of reliability at hierarchical level I (HL-I). This includes the ability of the generation to meet the total system load requirement [3] and to have the reserve margin capacity in order to serve for planned and forced outage events. It is also must be able to accurately meet up with the large fluctuations in the load from the result of a different quantity of power users[4, 17].  Power system reliability can be divided into two aspects, i.e., adequacy and security. System adequacy is related to the existing of appropriate generators within the system to cater the demand or the operational constraints and also to have an excess capacity to cater for planned and forced outage events that depended on the area under the load duration curve. In this paper, most widely used indices in electrical energy is presented, i.e., Loss of Energy Expectation (LOEE), Expected Energy Not Supplied (EENS) and the Energy Index of Load Reliability (EIR).

In [5],has presented a new fuzzy operationfor the area under the load duration curve model for evaluating reliability indices of composite power systems based on probability and fuzzy set methods.Meanwhile, in [6] has used fuzzy load description in generation, transmission power system reliability that using Monte Carlo method. A new hybrid approach to evaluate a generation system reliability using a fuzzy clustering approach in modeling the loads has been presented in [7]. Then, in [8] had proposed a genetic algorithm guided by fuzzy numbers to evaluate the power system reliability.

Hence, motivated by the reviews, this paper is tend to proposein the application of a fuzzy numbers approach to energy indices of power system based on the LOEE , EENS and EIR analysis. The proposed technique is then tested by using Malaysia distribution network (DISCO-Net) in MATLAB environment. The test results show by comparing the proposed technique with analytical method in order to help the engineers to measure and make decisions for assessment reliability power system.

2.Energy Reliability Indices

The most common methods used for reliability evaluation, are based on the loss of load or energy approach. In this method, the suitability index that describes generation reliability level is loss of energy expectation.It can be calculated the area under the load duration curve.It also indicates the time in which the load is more than available generation and can be used to calculate an expected energy not supplied [9,19]. In [10], By Billinton and Li (1994), The basic expected energy curtailed concept can also be used to determine the expected energy produced by each unit in the system and therefore provides a relatively simple approach to production cost modelling.

paper 5

Future electrical power systems may be energy limited rather than power or capacity limited, so we will study the ratio between the probable load energy curtailed because of reduced capacity because of specific capacity in outage and the total energy under the load duration curve can be defined as an energy index of unreliability. The energy index of reliability (EIR) is then as follows [11]:

1

3.Fuzzy Number

The arranging of fuzzy numbers plays an important role in decision making and optimization in power system reliability. The fuzzy approach must be derived before an action is taken by an engineer. In this paper, the special class of fuzzy numbers for load called triangular fuzzy numbers is used [12,16].The fuzzy set G is called a normal fuzzy set. A fuzzy number is a fuzzy method in the load that is both convex and normal. A type of fuzzy number of the load can be characterized by a triangular membership function parameterized by a triplet (L1, L2, L3), as shown in Fig. 1 [13].

2

3

4.Proposed Method

In this section, the proposed approach to electrical energy indicesevaluation is presented which takes the load duration under curve with probabilities capacity outage using a new fuzzy evaluation sheet.As an example, a generation system consists of 3 20 MW, that means, the estimation is based on 4 selected capacity outage as namely the generation 0, 20, 40 and 60 MW with identical weights of each state is w1, w2, w3 and w4 respectively, where wi ∈ [0,1] and i = 1, 2, 3 and 4. The value of the weight will be determined the degree of membership that obedience to load levels (Ls) and the probability (P1, P2, P3and P4) as shown in Fig. 2.

4

Each fuzzy load number is defined by three values of load to usetriangular fuzzy numbers [14,16] comprehensive effects of transmission line [18]. In Table I, The fuzzy numbers offered ten satisfaction levels in addition, area percentage of loads and the maximum degree of membership. Fainlly, the fuzzy evaluation sheet has four state (C1,C2,C3,C4) for capacity in service as shown in Table II.

5.png

6

The degree of satisfaction of the load (Ls) is calculated by equation (6) :

7

Where, dk Є [0,1] is a degree of fuzzy load and 1 ≤  k ≤ 4, The fuzzy load (Fl) for every state  can be calculated  by Equation (7):

8

Where, Load I = load demand, which requires an evaluation of the determined capacity in service, including larger values of capacity in service.

The demand not supplied (Dns) it is equal to energy curtailed by capacity in service. When the fuzzy load applied to implement the (Dns) this will result  into the  Equation (8):

9

Where,  ILT :  total  load demand under the load duration curve, h:  the duration of load power  in hours.

The equations  in section II above, i.e (1), (3) and (4) were used to assess losses of energy indices without fuzzy, in the subsequent Equations (9), (10) and (11), fuzzy load duration curve shall be used to evaluate these indices.

10

11

12

 

135.Description of Test System

The step down substation (in Malaysia is called main intake substation) is connected to the grid at nominal voltage of 132kV.  The maximum 3-phase and 1-phase-to-ground fault currents at the source are illustrated in Fig. 3 which means that on a 3-phase solid fault of the 132kV bus, the fault current, which is contributed by the source, is 20kA and 15kA on a single-phase to ground fault. The 132kV is stepped down to 11kV using 2x30MVA transformers and to 33kV using 2x45MVA transformers whose parameters are also illustrated in Fig. 3 (Network of DISCO-Net) [15]. This system has 33 buses with a 32 load bus, 45 transmission lines and 2 generating units 2x75MW. The total installed generating capacity is 150MW and the peak load of the system is 120MW. The data of generating units are given in Table III.This system was selected as a case study to implement the developed coding in order to analysis and determine electrical energy indices by fuzzy numbers and compared to an analytical method.

14

15

16

176.Result and Discussion

 First, in this study estimate, load duration curve for DISCO-Net is shown in Fig. 4. The total required energy in this duration is 8440 MWh. If there is no generation in the system, the expected energy not supplied would be 8440 MWh when the system has 75 MW.Table IV is shown an analytical method for the EENS with Unit 1, the value of expected energy not supplied is equal (2872.26 +395.604+53.46+8.44)  and the expected energy by unit (1) = 8440 – 3329.764 = 5110.236 MWh. From these results the energy index of the reliability EIR by unit (1) is 0.605478. The assistance from unit (2) can be obtained by adding 75 MW to the generation units of the Table IV and  resulting the expected energy not supplied for units (1) and (2) integrated (see Table V).In this case, the total EENS =19.3 and the expected energy by unit (2) is 5090.933 MWh.Finally, we can calculate EIR for the system using Equation(4), i.e.,EIR=1-(19.3/8440) = 0.9977132. Then, second proposedof the fuzzy number to compare the calculating results of the reliability energy indexes with analytical method.The fuzzy number has one membershipconsidering triangular fuzzy numbers for load duration curve shown in Fig.5.

For example, the column weights value in the Table V is obtained by simply dividing load with capacity in service, i.e.,80/100 = 0.8. This value 0.8, will then determine the degree of membership corresponding to the probabilities levels, from the results obtained in Table VI, the values, 0,0,0,0, 0.4,0.56,0.79 denotes the load level values at L1-L7 respectively. The values of energy and EENS were calculated with equations 6 and 7 which are the fuzzy load set that uses the central of the area. From table IV below, the same simulation was applied to the subsequent load levels, the EENS for each stage obtained were summed up to get 17.067 otherwise referred to herein as defuzzification value, thus denoting the expected energy not supplied.

From this result, the energy index of the reliability EIR is 0.997977 derived from equation 9.  Conclusively, it is clearly shown that the result obtained  with the use of EIR by fuzzy as energy indices assessment is close to the one derived when analytical method was used for same assessment.

7.Conclusion

This paper has been presented the application of a fuzzy numbers method to evaluate energy reliability indices based on a load duration curve and probabilities the capacity generators in service and compared with an analytical method in term of the expected energy not supplied and the energy index of the reliability for each state. It seems to be more near compared to results used in analytical approach.Therefore, this paper can help engineers to measure the reliability power system and make decisionsfor future process generation expansion planning.

REFERENCES

 [1]     Sidney J.Yakowitz.Computational Probability and Simulation. 3rd ed. Addison- Wesley Publishing Company: London; 1989.

[2]     R. E. Brown. Electric Power Distribution Reliability. 2nd ed. New York: Marcel Dekker; 2002.

[3]     Wijarn Wangdee. Bulk electric system reliability simulation and application. PhD thesis. Department of Electrical Engineering, University of Saskatchewan, Canada S7N 5A9, 2006.

[4]     Devendra K. Chaturvedi.  Soft Computing Techniques and its Applications in Electrical Engineering.Vol 103. Springer-Verlag Berlin Heidelberg, 2008.

[5]     Choi ,J. et al. ,A study on the fuzzy ELDC  of  a composite power system based on probabilistic and fuzzy set theories, IEEE power Engineering society summer meeting ,2002, vol .3,pp.1123_1129.

[6]     Saraiva ,J.T.et al., Generation /transmission power system reliability evaluation  by monte carlo simulation assuming a fuzzy load description, IEEE Trans,1996,,Vol.2 , pp. 690_695.

[7]     Narasimhan , S.and Asgarpoor ,S., Including uncertainty in LOLE calculation using fuzzy set theory , IEEE Trans. On power systems,2000 , Vol.45, pp.133_138.

[8]     Samaan , N. and Singh, C., state evaluation in composite power system reliability using genetic algorithm guided by fuzzy constraints in proceedings of the international conf.,2002, Vol.1,pp.409_414.

[9]     Billinton, R. and R. Allan, 1996. Reliability Evaluation of Power Systems. Second Edition.New York: Plenum Press 2002.

[10]   Billinton, R. and W. Li, Reliability assessement of electrical power system using Monte Carlo Methods, Springer, New York, 1994.

[11]   Marko C epin. Assessment of power system reliability methods and applications. Springer-Verlag;2011.

[12]   A.K.Verma, A.Srividya and R.Sprabhu. Fuzzy reliability   Engineering, .           New Delhi ,Narosa, 2007.

[13]   Kaufmann,A, Introduction to the theory of fuzzy Subsets ,Vol.1, NEW York, 1975.

[14]   H.-J. Zimmermann, Fuzzy Set Theory and Its Applications. Dordrecht, The Netherlands: Kluwer-Nijhoff, 1991.

[15]   “Electrical Power System Competition 2009   “    EPSCOM 2009, 40675 Shah Alam, Selangor 2009 in January 2009 at Universiti Kebangsaan Malaysia.

[16]   Shalash, Nadheer A., and Abu Zaharin Ahmad. ” Agents for

fuzzy indices of reliability power system with uncertainty using Carlo algorithm.” Power Engineering and Optimization Conference (PEOCO), 2014 pp. 258 – 264. IEEE, 24-25 March 2014.

[17]   Vladislav O.,   Svyatoslav T. , Anna B.  and Sergey Gusev.”Stochastic Network Reduction Technique for Calculations of   Electrical Power System Structural Reliability ”  Second International Symposium on Stochastic Models in Reliability Engineering (SMRLO),   pp. 144 – 149. IEEE, 15-18 Feb

 

 

 

 

 

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 Applications of Floating-gate MOSFET in the design of inverter and ring oscillator

Roshani Gupta, Rockey Gupta and Susheel Sharma

 Department of Physics and Electronics, University of Jammu, Jammu-180006, India

 Abstract

This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance the performance of  inverter in terms of various parameters like switching threshold voltage, noise margins, propagation delay and energy delay product. It has been observed that by varying the bias voltage in FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V. 

Keywords

Floating-gate MOSFET, inverter, voltage transfer characteristics, propagation delay, energy delay product, ring oscillator

1.Introduction

The design of digital integrated circuits with very low power consumption and without much degradation in speed has always been the focal point of researchers particularly in sub-micron regime [1-3]. Since there is always a trade-off between power dissipation and time delay, therefore, reducing the power dissipation and still maintaining the appreciable performance in terms of operating speed is much desirable. With the immense demand of portable and battery driven applications, there is a need for new and alternative circuit design techniques to implement high performance and low power digital circuits. Further, with reducing feature size of devices, the lowering of operating supply voltage is obvious but at the expense of speed. Hence, for optimum performance of digital circuits, alternative design techniques should be explored [4-6].

CMOS inverter forms a basic building block of digital sub-circuits in mixed mode circuits with limitation of high switching threshold voltage resulting in degraded performance. Floating-gate MOSFET (FGMOS) has been widely used in the design of low voltage analog and digital circuits due to its unique characteristic of threshold voltage tuning with a bias voltage, thus imparting enhancement in performance. In this paper, we have employed floating-gate MOSFET (FGMOS) to design an inverter which has been further used to implement a ring oscillator. The paper has been divided in various sections briefly introducing FGMOS, its application in the design of inverter and ring oscillator. The performance of the designed circuits has been found to be enhanced vis-à-vis their conventional CMOS versions. The workability of these circuits has been verified through PSpice simulations carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.

2.Floating-Gate MOS transistor

The Floating-Gate MOS transistor (FGMOS) is basically a modified form of simple MOSFET where extra capacitances have been introduced between the conventional gate and the multi-input signal gates. By applying a bias voltage on one of the input gates, the threshold voltage of FGMOS can be reduced. A number of secondary gates or input terminals are deposited above the floating-gate (FG) which are electrically isolated from it but capacitively connected to it. Since FG is completely surrounded by highly resistive material, so for dc operation, FG acts as floating node. Programming of the FGMOS introduces a charge on its floating-gate that shifts the threshold voltage and thus, provides a control over the device functionality [7-10]. The equivalent schematic for an N-input and n-channel FGMOS is shown in Fig. 1 [11].

1

In a two-input n-channel FGMOS, input voltage (Vin) is applied through C1 and bias voltage (Vbias) is applied through C2 which provides tunability to the conventional threshold voltage (VT) of the FGMOS and VT adjusts to a new value VT,eff   given as [12]:

2

where  and  and C1 and C2 are the capacitances between floating-gate and control gates and. We observe that VT,eff will be less than VT  if we select Vbias > VT and k2 >k1, implying C2>C1. Thus, in FGMOS we can select VT,eff lower than normal VT.

Now, by selecting W/L of FGMOS as 1.3µm/0.13µm and with supply voltage of 1V, the drain and transfer characteristics are shown in Figs. 2 and 3 respectively.

3

It has been observed that as we increase Vbias from 0.3V to 0.6V, effective threshold voltage (VT,eff) of n-channel FGMOS decreases from 0.8V to 0.2V at a reference drain current of 20 µA. Similarly, the drain and transfer characteristics for p-channel FGMOS show bias dependent behaviour. Thus, the performance of n-channel and p-channel FGMOS can be varied by optimum selection of their respective Vbias and making FGMOS based digital circuits suitable for low voltage and low power applications.

3.FGMOS Inverter

The architecture of the FGMOS inverter has been obtained from the conventional CMOS inverter as shown in Fig. 4 [13]. The bias voltages Vbp and Vbn provide tunability to the threshold voltages of M1 and M2 respectively. It is, therefore, expected that by varying the bias voltages, the threshold voltage of the FGMOS inverter can be changed.

4

The performance of FGMOS inverter can be characterized through its voltage transfer characteristics (VTC) which is a plot of Vout as a function of Vin. From these characteristics we can calculate parameters like switching threshold voltage and noise margins to ascertain the dc performance of these circuits. The switching threshold voltage (VS) is defined as the input voltage that gives an identical output voltage and it can be obtained from the intersection of the VTC curve and the plot of Vout = Vin [13, 14]. The voltage noise margins can be obtained as NMH = VOHVS and NML = VS VOL, where VOH and VOL are logic-high and logic-low output voltages of inverter respectively. Since noise margins NMH and NML account for the sensitivity of a gate to noise, therefore large value of this parameter is desired that makes the gate less sensitive to noisy environment [15].

The switching threshold voltage for FGMOS inverter is given by [14]:

5

Now, the circuit of FGMOS inverter has been simulated to obtain the voltage transfer characteristics (VTC) at different values of Vbp and Vbn  by selecting W/L of M1 as 26 μm/0.13 μm and M2 as 13 μm/0.13 μm with a supply voltage of 1 V as shown in Figs. 5 and 6 respectively.

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From Figs. 5 and 6, the calculated values of the switching threshold voltage (VS) and noise margins NMH and NML at different values of Vbp and Vbn are given in table 1.

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As observed in table 1, when bias voltage of p-channel FGMOS (Vbp) is varied from 0 V to 1 V at constant bias voltage of n-channel FGMOS (Vbn = 1V), the switching threshold voltage (VS) and low noise margin (NML) of FGMOS inverter decreases from 0.40 V to 0.21 V but high noise   margin (NMH) increases from 0.60 V to 0.79 V. Similarly, when bias voltage of n-channel FGMOS (Vbn) is increased from 0 V to 1 V, while keeping Vbp fixed at 0 V, NML decreases from 0.68 V to 0.40 V. Now, in the circuit of FGMOS inverter, M2 (n-channel) determines NML and M1 (p-channel) determines NMH and both noise margins are desired to be high for better noise immunity. From table 1, we observe that NMH and NML are maximum when Vbp = 0 V & Vbn = 1 V which is the condition of low voltage operation for FGMOS because for Vbp = 0 V & Vbn = 1 V, M1 and M2 exhibits minimum value of threshold voltage. Therefore, better noise margins can be optimized by appropriate selection of Vbp and Vbn at 0V and 1V respectively.

The transient behaviour of the FGMOS inverter can be characterized by propagation delay (tp) which is defined as the average of the time delay from low-to-high transition (tplh) and from high-to-low transition (tphl) of the input and output waveforms in an inverter. It specifies the operating speed and is given as [15, 16]:

8

Since tp depends on threshold voltage of n and p-channel MOSFETs, therefore it is expected that it can be optimized using FGMOS where threshold voltage tunability is feasible [12].

The transient characteristics of FGMOS inverter at different values of Vbp and Vbn are shown in Figs. 7 and 8 respectively.

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It is seen that the pulse response of FGMOS inverter can be varied with bias voltage resulting in different values of propagation delay as shown in Fig. 9.

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It has been observed in Fig. 9 that if the bias voltage of p-channel FGMOS is increased from 0V to 1V while keeping bias voltage of n-channel FGMOS fixed at 1 V, the propagation delay increases from 0.19 ns to 0.66 ns. Similarly, if bias voltage of n-channel FGMOS is increased from 0 V to 1 V while keeping bias voltage of p-channel FGMOS fixed at 0 V, the propagation delay decreases from 0.32 ns to 0.19 ns. Therefore, the appropriate selection of bias voltages of n and p-channel FGMOS at 1V and 0V respectively decreases the propagation delay of FGMOS inverter, thus enhancing the operating speed.

Now, the comparative transient characteristics of CMOS and FGMOS inverters have been obtained by selecting Vbp = 0 V and Vbn = 1 V as shown in Fig. 10.

12

From these results, it has been observed that FGMOS based inverter has less propagation delay (0.2 ns) as compared to CMOS inverter which has the propagation delay of 0.4 ns, implying that FGMOS based inverter exhibits better switching response and has high operating speed.

Since, the energy delay product represents the trade-off between power dissipation and the speed, implying the operation of digital circuits at low power would result in loss of speed. Therefore, lower value of energy delay product is required for circuits suitable for operation with low operating voltage and low power consumption without much loss in operating speed. Now, the values of propagation delay obtained from the transient analysis of CMOS and FGMOS based inverters has been used to calculate the energy delay product (EDP) at different values of VDD as shown in Fig. 11.

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The results obtained from Fig. 11 show that EDP is a function of supply voltage and for VDD=1V, FGMOS inverter has EDP of 1×10-23 Js where as the value of EDP for CMOS inverter is 2×10-23 Js.  Therefore, FGMOS inverter shows better performance as compared to CMOS due to lower value of energy delay product, thus posing as an alternative design technique for low voltage and high speed digital circuits.

4.Ring Oscillator

Since FGMOS inverter exhibits better response than its CMOS counterpart in terms of speed, noise immunity and power dissipation, therefore it has been further employed to implement a ring oscillator which is often used in the information, communication and sensor technology for frequency translation and channel selection [17-19].

A ring oscillator based on FGMOS is shown in Fig. 12 which consists of a cascade of three inverters and the frequency of oscillation is given by [20]:1415

From Eq. 8, we see that propagation delay decreases with increase in Vbn and decrease in Vbp. Therefore, increasing bias voltage of n-channel FGMOS while keeping bias voltage of p-channel FGMOS at zero volt will lead to small propagation delay and hence, enhanced frequency of oscillation. Now, the circuit of FGMOS ring oscillator has been simulated at different values of Vbn while keeping Vbp fixed at 0 V by selecting W/L of M1, M3 and M5 as 26μm/0.13μm and M2, M4 and M6 as 13μm/0.13μm with the supply voltage of 1 V. The simulation results are shown in Fig. 13.

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From the above results we have observed that the frequency of oscillation increases with increase in bias voltage (Vbn) as shown in table 2.

17

The comparative performance of CMOS and FGMOS based three stage ring oscillator has been obtained by selecting Vbp = 0 V and Vbn =1 V and is shown in Fig. 14. It has been observed that frequency of oscillations in FGMOS ring oscillator is 6.7 GHz while for CMOS ring oscillator it is 5 GHz.

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The number of inverter stages in ring oscillator may be increased for multiphase outputs but at the expense of reduced operating speed, high power dissipation and large chip area [20]. The comparative frequency of oscillations in ring oscillator using CMOS and FGMOS with different stages is given in table 3

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From the above results, we observe that with increase in the number of inverter stages in the structure of ring oscillator, the frequency of oscillation decreases due to increased propagation delay.

5.Conclusions

In this paper, we have studied the effect of threshold voltage tunability in FGMOS for enhancing the performance of inverter and ring oscillator. It has been found that by varying the bias voltage of FGMOS, the voltage transfer characteristics of inverter can be suitably altered resulting in decreased switching threshold voltage, increased noise margins, reduced propagation delay and energy delay product as compared to its CMOS version. Further, it has been observed that the oscillation frequency of ring oscillator depends on the propagation delay of inverter stages and FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to CMOS ring oscillator.

References

[1]     A. P. Chandrakasan, S. Sheng  & R. W. Brodersen, (1992) “Low power CMOS digital design”,               IEEE J. Solid-State Circuits, Vol. 27, No. 4, pp. 473-484.

[2]     R. Gonzalez, B. M. Gordon & M. A. Horowitz, (1997) “Supply and threshold voltage scaling for low power CMOS”, IEEE J. Solid-State Circuits, Vol. 32, No. 8, pp. 1210-1216.

[3]     E. S. Sinencio & A. G. Andreou, (1997) “Low-Voltage/Low-Power Integrated Circuits and Systems”, IEEE Press.

[4]     S. Yan & E. S. Sinencio, (2000) “Low Voltage Analog Circuit Design Techniques: A Tutorial”, IEICE Trans. Analog Integrated Circuits and Systems, Vol. E00-A, No. 2, pp. 1-17.

[5]     C. J. B. Fayomi, M. Sawan & G. W. Roberts, (2004) “Reliable Circuit Techniques for Low Voltage Analog Design in Deep Sub micron Standard CMOS: A Tutorial”, Analog Integr. Circuits Signal Proc., Vol. 39, No.1, pp. 21-38.

[6]     J. R. Angulo, S. C. Choi & G. G. Altamirano, (1995) “Low voltage circuits building blocks using multiple input floating gate transistors”, IEEE Trans. Circuits Syst.-I, Vol. 42, No. 11, pp. 971-974.

[7]     J. R. Angulo, G. G. Altamirano & S. C. Choi, (1997) “Modeling multiple-input floating-gate transistors for analog signal processing”, Proc. IEEE Int. Symp. Circuits Syst., Vol. 3, pp. 2020-2023.

[8]     P. Hasler & T. S. Lande, (2001) “Overview of floating-gate devices, circuits and systems”, IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, Vol.48, No.1, pp. 1-3.

[9]     E. R. Villegas, (2006) Low Power and Low Voltage Circuit Design with FGMOS Transistor, IET Circuits, Devices and Systems, Series 20.

[10]   M. Gupta & R. Pandey, (2010) “FGMOS based voltage-controlled resistor and its applications”, Microelectronics Journal, Vol. 41, pp. 25-32.

[11]   A. Kumar, (2013) “Split length FGMOS MOS cell: a new block for low voltage applications”,   Analog Integrated Circuits and Signal Processing, Vol. 75, pp. 399-405.

[12]   S. Sharma, S. S. Rajput, L. K. Mangotra & S. S. Jamuar, (2006) “FGMOS current mirror: behavior and bandwidth enhancement”, Analog Integrated Circuits and Signal Processing, Vol. 46 pp. 281-286.

[13]   J. Rabaey, A. Chandrakasan & B. Nikolic, (2003) Digital Integrated circuits, A Design Perspective, Prentice Hall.

[14]   J. P. Uyemura, (2002) Introduction to VLSI circuits and systems, John Wiley and sons, New Delhi.

[15]   K. Martin, (2000) Digital Integrated circuit design, Oxford university press.

[16]   B. Razavi, (2008) Fundamentals of Microelectronics, John Wiley and sons.

[17]   C. H. Park, O. Kim & B. Kim, “A 1.8-GHz self-calibrated phase locked loop with precise I/Q matching”, IEEE J. Solid-State Circuits, Vol. 36, pp. 777-783, 2001.

[18]   J. Savoj & B. Razavi, (2001) “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector”, IEEE J. Solid-State Circuits, Vol. 36, pp. 761-767.

[19]   M. Alioto & G. Palumbo, (2001) “Oscillation frequency in CML and ESCL ring oscillators”, IEEE Trans. Circuits Syst. I, Vol. 48, pp. 210-214.

[20]   M. K. Mandal & B. C. Sarkar, (2010) “Ring oscillators: characteristics and applications”, Indian journal of Pure and Applied Physics, Vol. 48, pp. 136-145.

AUTHORS

Susheel Sharma received his MSc Physics (Electronics) from University of Jammu, Jammu, India in 1991 and PhD degree from the same University in 2007 on the title ‘Analog applications of Floating-Gate MOS transistor in current mirrors and current conveyors’.20 He has been working as faculty in the Department of Physics & Electronics, University of Jammu since 1995. Presently he is an Associate Professor in Electronics and his area of research interest includes Low voltage analog and digital integrated circuits and he has 44 publications to his credit in various National/International conferences and journals. He is a life member of Institution of Electronics and Telecommunication Engineers (IETE) India and Indian Science Congress.

Rockey Gupta received his M.Sc. degree  in Electronics from University of Jammu in 2000 with gold medal. He received his Ph. D degree in Electronics in 2014 from the same university. He has been working as a faculty member in the department of Physics and Electronics since March 2002. He has been teaching courses of electronic devices and circuits, digital electronics, IC technology, microprocessors and microcontrollers and 21computer programming with c++ to M.Sc electronics students. He is a life member of Institution of Electronics and Telecommunication Engineers (IETE) India and Indian Science Congress. Presently he is working as a senior Assistant Professor in Department of Physics and Electronics, University of Jammu. His area of research includes low voltage analog circuit design techiques using quasi-flaoting-gate MOSFETs. He has 20 publications to his credit in various National/International conferences and journals.

Roshani Gupta received her M.Sc. and M.Phil. in Electronics from University of Jammu in the years 2011 and 2014, respectively. Presently she is pursuing Ph.D. in Electronics from the same University. Her research interests include designing CMOS digital circuits for low22 power applications.

 

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Single Phase Symmetrical Multilevel Inverter Design For Various Loads

 C.R.Balamurugan1 , S.P.Natarajan2 and T.S.Anandhi3

 1 Department of EEE, Arunai Engineering College, Thiruvannamalai, Tamilnadu, India

and

2,3 Department of EIE, Annamalai University, Chidambaram, Tamilnadu, India

Abstract

This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology has less number of switches than the conventional one. In conventional cascaded multilevel inverter have twelve switches and the proposed topology have eight switches. Totally the four switches have been reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis has been done by a MATLAB/SIMULINK model.

 Keywords

Total Harmonic Distortion, Pulse Width Modulation, Cascaded multilevel inverter, Induction Motor.

1.Introduction

MLIs have been drawing growing attention in the recent years especially in the distributed energy resources area because several batteries, fuel cells, solar cells or rectified wind turbines or micro turbines can be connected through a MLI to feed a load or interconnect to the AC grid without voltage balancing problems. The unique structure multilevel VSIs allow them to reach high voltages with low harmonics without the use of transformers. This makes these unique power electronic topologies suitable for FACTS and custom power applications. The unique structure multilevel VSIs allow them to reach high voltages with low harmonics without the use of transformers. This makes these unique power electronic topologies suitable for FACTS and custom power applications. Holmes et al [1] introduced opportunities for Harmonic Cancellation with Carrier Based PWM for two level and multilevel cascaded inverters. Rodriguez et al [2] this paper presents the most relevant control and modulation methods developed for this family of converters multilevel sinusoidal pulse width modulation, multilevel selective harmonic elimination, and space-vector modulation Li et al [3] proposed a real time testing of a controller for multi bus micro grid system. Tallam et al [4] introduced a carrier-based PWM scheme for neutral-point   voltage balancing in three-level inverters. Leppanen et al [5] suggested the observer using low-frequency Injection for Sensor less Induction Motor Control-Parameter Sensitivity Analysis. McGrath et al [6] proposed a new multilevel inverter shows reduction in the total harmonics upto 60 percentage.Rodriguez et al [7] proposed multilevel voltage source converter topologies for industrial medium voltage drives. Zhong et al [8] deals with a DC-AC cascaded H-bridge multilevel boost inverter with no inductors for electric/hybrid electric vehicle applications. Lezana et al [9] describes a survey on fault operation on multilevel inverters.

Malinowski et al [10] describes a survey on cascaded multilevel inverters. Sepahvand et al [11] developed a capacitor voltage regulation in cascaded H-bridge multilevel converters with fundamental frequency switching.  Ehsan Najafi et al [12] proposed a new multilevel inverter topology with various carrier based techniques and the various analysis also done for this topology.  Balamurugan et al [13] presents various PWM techniques and the IM gives the fewer harmonic compared to other techniques. Saipadhma et al [14] deals with the voltage control strategy fundamental switching and Sinusoidal Pulse Width Modulation of the conventional cascaded inverter topology is compared with the new reverse voltage topology. Srinivas Reddy Chalamalla [15] introduced a new technique with an induction motor drive which produces a low switching frequency.

2.Cascaded Multilevel Inverter

The problem of eliminating harmonics in inverter has been focus of research for many years. To reduce the harmonics different multilevel SPWM and SVPWM schemes are suggested in the literature however these PWM techniques increase the control complexity and switching frequency. In selective harmonic elimination or programmed harmonic elimination method the switching angles are chosen or programmed to eliminate specific harmonics. The power circuit Fig.1 consists of a cascade of N independent single-phase inverters. Using the top FBI as the example, turning on S11 and S41 yields +Vdc output. Turning on S21 and S31 yields -Vdc output. Turning off all switches yields  0 volts output. The AC output voltage at other FBIs can be obtained in the same manner. The number of voltage levels at the load generally defines the number of FBIs in cascade. The number of FBI units or DC sources N is (m-1)/2 where m is the sum of zero level and the number of positive and negative levels in MLI output. Each switching component turns on and off only once per cycle i.e. at the line frequency. The main features of cascaded multilevel inverters are:

  • It can generate almost sinusoidal output voltage while switching only one time per fundamental cycle.
  • It can eliminate transformers of multi-pulse inverters used in conventional utility interfaces and static VAR compensators.12

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3.Proposed Multilevel Inverter

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Fig. 2 shows the proposed seven level inverter circuits. This proposed method is different from the method since it does not have any bidirectional switch and different from the method since it has less number of switches.

PWM techniques are employed in inverters to achieve high quality output voltage of desired amplitude and frequency which are as close as possible to sinusoidal wave. Power electronics researchers have many control techniques to reduce harmonics in such cases. Table 1 shows the switching pattern

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4.Simulation Output and Results

The MATLAB simulation circuit was developed for proposed seven levels inverter with various loads.

4.1. Proposed Circuit With R-Load

The circuit consists of 12 switches with three equal dc sources. The load has been used as a resistive load. In the SIMULINK circuit pulses are generated by using pulse generators only. For each H-bridge two pulses are generated for two pairs of switches. This means that two opposite switches in each H-bridge is turned ON and OFF at the same instant of time. The simulation circuit for a proposed multilevel inverter with R load has been shown below. By using this simulation circuit the harmonics and output voltage analysis has been done. It has been shown in below figure 4 and 5.

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 3.2. Proposed circuit with RL-load

The proposed circuit consist of RL load in a output side of a simulation circuit. This simulation circuit is used to analyse the harmonics and the output voltage. Fig. 6 to 8 shows the sample simulink model, output voltage and FFT plot.

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3.3. Proposed Circuit With Induction Motor

The proposed circuit consist of induction motor load in an output side of a simulation circuit. The simulation circuit is shown in a below figure 9.

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174.Conclusions

In this paper the simulation results of single phase seven level cascaded multilevel inverter with R, RL and Induction Motor load are analysed by using MATLAB/SIMULINK. The output quantities like phase voltage, THD spectrum for a various load are obtained. The torque-speed characteristics of induction motor are also obtained. From Table 2 and 3 the cascaded multilevel inverter with R-load gives less %THD and it perform better than RL load and induction motor load. Depends upon the need of load we can use this cascaded multilevel inverter for various applications.

References

  • Holmes, D. G. and Brendan, P. M. (2001) “Opportunities for Harmonic Cancellation with Carrier Based PWM for two level and Multilevel Cascaded Inverters”, IEEE Trans. Ind. Appl., Vo1. 37, No. 2, pp. 574-582.
  • Rodriguez, J., Lai, J. S., and Peng, F. Z., (2002) “Multilevel inverters:A survey of toplogies, controls and applications,” IEEE Trans.Ind. Electron., 49, No. 4, pp. 724–738.
  • Li, D. M. Vilathgamuwa, and P. C. Loh,( 2004) ―Design, analysis, and real time testing of  a  controller for multi bus micro grid system”, IEEE Trans. Power Electronics, vol. 19, no. 5, pp. 1195-1204.
  • M. Tallam, R. Naik, and T. A. Nondahl,(2005) “A carrier-based PWM scheme for neutral-point voltage balancing in three-level inverters,” IEEE Trans.Ind. Appl., vol. 41, no. 6, pp. 1734–1743.
  • Leppanen, V. M. and Luomi, M.,(2006) “Observer Using Low-frequency Injection for Sensor less Induction Motor Control-Parameter Sensitivity Analysis”, IEEE Trans. Ind. Appl., Vol. 53, No.1,pp. 216-224.
  • P.McGrath, D.G.Holmes and T.Meynard,(2006) “Reduced PWM harmonic distortion for multilevel inverter operating over a wide modulation range‟, IEEE Trans. on Power Electron., Vol. 21, pp. 941–949.
  • Rodriguez, J., Bernet, S., Pontt, J. O. and Kouro,S. (2007) “Multilevel Voltage Source Converter Topologies for Industrial Medium VoltageDrives”, IEEE Trans. Ind. Electron.,   vol. 54, No. 6, pp. 290-294.
  • Zhong, B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, (2009) “DC-AC cascaded H-bridge multilevel boost inverter with no inductors for electric/hybrid electric vehicle applications”, IEEE Trans. Ind. Appl., vol. 45,no. 3, pp. 963–970.
  • Lezana, J. Pou, T. A. Meynard, J. Rodriguez, S. Ceballos, and F. Richardeau,(2010) “Survey on fault operation on multilevel inverters”, IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2207–2218.
  • Malinowski, K. Gopakumar, J. Rodriquez, and M. Perez,(2010) “A survey on cascaded multilevel inverters”, IEEE Trans. Ind. Electron., vol. 57, no. 7,pp. 2197–2206.
  • Sepahvand, H., Liao, J., Ferdowsi, M.(2011)”Investigation on capacitor voltage regulation in cascaded H-bridge multilevel converters with fundamental frequency switching”, IEEE Trans. Ind. Electron.,58, no.11, pp. 5102–5111.
  • Ehsan Najafi and Abdul Halim Mohamed Yatim, (2012)”Design   and Implementation of a New Multilevel Inverter Topology”, IEEE Trans. Ind. Electron., vol. 59, no. 11.
  • R. Balamurugan, S. P. Natarajan and R.Bensraj, (2012)”performance and Evaluation of Three Phase Bridge Module Type Diode Clamped Multilevel Inverter”, International Journal of Engineering Trends and Technology, Vol.3, No.3, pp.380-389.
  • S, Sangeetha.S and Kannabiran.A, (2013)” Comparison of Modulation Techniques             for Cascaded and Reverse Voltage Multilevel Inverter Topologies”, International Journal of Advanced Trends in Computer Science and Engineering, Vol.2, No.2, pp . 261- 266.
  • Srinivas Reddy Chalamalla and S.Tara Kalyani,(2013) “Analysis of IM Fed by Multi-carrier SPWM and Low Switching Frequency Mixed CMLI”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering,2,No.12,pp. 6295-6302.

 

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 Important Dates

  • Submission Deadline    : September 04, 2016

  • Notification           :  October 04, 2016

  • Final Manuscript Due    : October 12, 2016
  • Publication Date            : Determined by the Editor-in-Chief
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